 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| www..com Micron Confidential and Proprietary Advance 1Gb: x8, x16 NAND Flash Memory Features 1Gb NAND Flash Memory MT29F1GxxABB For the latest data sheet, refer to Micron's Web site: www.micron.com/datasheets Features * Organization * Page size x8: 2,112 bytes (2,048 + 64 bytes) * Page size x16: 1,056 words (1,024 + 32 words) * Block size: 64 pages (128K + 4K bytes) * Device size: 1Gb: 1,024 blocks * READ performance * Random READ: 25s (MAX) * Sequential READ: 50ns (MIN) * WRITE performance * PROGRAM PAGE: 300s (TYP) * BLOCK ERASE: 2.0ms (TYP) * Endurance: 100,000 PROGRAM/ERASE cycles * Data retention: 10 years * The first block (block address 00h) is guaranteed to be valid without ECC (up to 1,000 PROGRAM/ERASE cycles). * VCC: 1.65V-1.95V * Automated PROGRAM and ERASE * Basic NAND Flash command set * PAGE READ, RANDOM DATA READ, READ ID, READ STATUS, PROGRAM PAGE, RANDOM DATA INPUT, PROGRAM PAGE CACHE MODE, INTERNAL DATA MOVE, INTERNAL DATA MOVE with RANDOM DATA INPUT, BLOCK ERASE, RESET * New commands * PAGE READ CACHE MODE * READ ID2 (contact factory) * READ UNIQUE ID (contact factory) * Programmable I/O * OTP * BLOCK LOCK * Operation status byte: Provides a software method for detecting: * Operation completion * Pass/fail condition * Write-protect status * Ready/busy# pin (R/B#) * Provides a hardware method of detecting operation completion * LOCK signal: Protects selectable ranges of blocks * WP# signal: Write-protects the entire device PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__1.fm - Rev. 2.0 6/06 EN Figure 1: 63-Ball VFBGA x8 Options1 * Configuration * x8 * x16 * Package * 63-ball VFBGA 13mm x 10.5mm x 1.0mm * Operating temperature * Commercial temperature (0 to +70C) * Extended temperature (-40C to +85C) Notes: 1. For part numbers and device markings, see Figure 2 on page 2. 1 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by Micron without notice. Products are only warranted by Micron to meet Micron's production data sheet specifications. Draft 6/ 28/ 2006 www..com Micron Confidential and Proprietary Advance 1Gb: x8, x16 NAND Flash Memory Part Numbering Information Part Numbering Information Micron NAND Flash devices are available in several different configurations and densities (see Figure 2). Figure 2: Part Number Chart MT 29F 1G Micron Technology Product Family 29F = Single-Supply NAND Flash Memory 08 A B B HC xx xx xx ES :B Die Revision B = Second genertion Density 1G = 1Gb Production Status Blank = Production ES = Engineering Sample QS = Qualification Sample Device Width 08 = 8 bits 16 = 16 bits Operating Temperature Range Blank = Commercial (0C to +70C) ET = Extended (-40 to +85C) # of die # of CE# # of R/B# I/O A 1 1 1 Common Block Option Reserved for Future Use Operating Voltage Range B = 1.8V (1.65V-1.95V) Flash Performance Reserved for Future Use Feature Set A = Feature set A B = Feature set B Package Codes HC = 63-pin VFBGA (lead-free) Valid Part Number Combinations After building the part number from the part numbering chart, please go to the Micron Parametric Part Search Web site at http://www.micron.com/products/parametric to verify that the part number is offered and valid. If the device required is not on this list, please contact the factory. PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__1.fm - Rev. 2.0 6/06 EN 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Draft 6/ 28/ 2006 Classification www..com Micron Confidential and Proprietary Advance 1Gb: x8, x16 NAND Flash Memory Table of Contents Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Part Numbering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 Valid Part Number Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Memory Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Address Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 READs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 READY/BUSY# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Command Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 READ Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 PAGE READ 00h-30h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 RANDOM READ 05h-E0h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 PAGE READ CACHE MODE START 31h; PAGE READ CACHE MODE START LAST 3Fh. . . . . . . . . . . . . . . . . .23 READ ID 90h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 ONFI READ ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 ONFI READ PARAMETER PAGE Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 READ STATUS 70h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 PROGRAM Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 PROGRAM PAGE 80h-10h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 SERIAL DATA INPUT 80h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 RANDOM DATA INPUT 85h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 PROGRAM PAGE CACHE MODE 80h-15h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 INTERNAL DATA MOVE Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 READ FOR INTERNAL DATA MOVE 00h-35h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 INTERNAL DATA MOVE 85h-10h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 BLOCK ERASE 60h-D0h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 One-Time Programmable (OTP) Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 OTP DATA PROGRAM A0h-10h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 OTP DATA PROTECT A5h-10h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 OTP DATA READ AFh-30h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Block Lock Feature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 WP# and Block Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 UNLOCK 23h-24h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 LOCK 2Ah . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 LOCK-TIGHT 2Ch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 BLOCK LOCK READ STATUS 7Ah . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 RESET Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 RESET FFh. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 Programmable Drive Strength. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 PROGRAMMABLE I/O DRIVE STRENGTH B8h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 WRITE PROTECT Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Error Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 VCC Power Cycling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 Timing Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48aTOC.fm - Rev. 2.0 6/06 EN 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Draft 6/ 28/ 2006 www..com Micron Confidential and Proprietary Advance 1Gb: x8, x16 NAND Flash Memory List of Figures List of Figures Figure 1: Figure 2: Figure 3: Figure 4: Figure 5: Figure 6: Figure 7: Figure 8: Figure 9: Figure 10: Figure 11: Figure 12: Figure 13: Figure 14: Figure 15: Figure 16: Figure 17: Figure 18: Figure 19: Figure 20: Figure 21: Figure 22: Figure 23: Figure 24: Figure 25: Figure 26: Figure 27: Figure 28: Figure 29: Figure 30: Figure 31: Figure 32: Figure 33: Figure 34: Figure 35: Figure 36: Figure 37: Figure 38: Figure 39: Figure 40: Figure 41: Figure 42: Figure 43: Figure 44: Figure 45: Figure 46: Figure 47: Figure 48: Figure 49: Figure 50: Figure 51: Figure 52: Figure 53: Figure 54: Figure 55: Figure 56: 63-Ball VFBGA x8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Part Number Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 Functional Block Diagram: 1Gb NAND Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Ball Diagram (x8), 63-Ball VFBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Ball Diagram (x16), 63-Ball VFBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Array Organization for MT29F1G08 (x8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Array Organization for MT29F1G16 (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Memory Map x8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Memory Map x16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Time Constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Minimum Rp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 READY/BUSY# Open Drain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 tFall and tRise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Iol vs. Rp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 TC vs. Rp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 PAGE READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 RANDOM DATA READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 PAGE READ CACHE MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 READ ID Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 ONFI READ ID Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 ONFI READ PARAMETER PAGE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Status Register Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 PROGRAM and READ STATUS Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 RANDOM DATA INPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 PROGRAM PAGE CACHE MODE Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 INTERNAL DATA MOVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 INTERNAL DATA MOVE with RANDOM DATA INPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 BLOCK ERASE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 OTP DATA PROGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 OTP DATA PROTECT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 OTP DATA READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Flash Array Protected: Inverted Area Bit = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Flash Array Protected: Invert Area Bit = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 UNLOCK Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 LOCK Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 LOCK-TIGHT Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 PROGRAM/ERASE Issued to Locked or Locked-Tight Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 LOCKED-TIGHT BLOCKS to LOCKED BLOCKS Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 BLOCK LOCK READ STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 BLOCK LOCK Flow Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 RESET Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 Programmable I/O Drive Strength Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 ERASE Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 ERASE Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 PROGRAM Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 PROGRAM Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 AC Waveforms During Power Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 COMMAND LATCH Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 ADDRESS LATCH Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 INPUT DATA LATCH Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 SERIAL ACCESS Cycle after READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 SERIAL ACCESS Cycle After READ (EDO Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 READ STATUS Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 PAGE READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 READ Operation with CE# "Don't Care" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 RANDOM DATA READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48aLOF.fm - Rev. 2.0 6/06 EN Draft 6/ 28/ 2006 www..com Micron Confidential and Proprietary Advance 1Gb: x8, x16 NAND Flash Memory List of Figures Figure 57: Figure 58: Figure 59: Figure 60: Figure 61: Figure 62: Figure 63: Figure 64: Figure 65: Figure 66: Figure 67: Figure 68: Figure 69: Figure 70: PAGE READ CACHE MODE Timing Diagram, Part 1 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 PAGE READ CACHE MODE Timing Diagram, Part 2 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 PAGE READ CACHE MODE Timing without R/B#, Part 1 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 PAGE READ CACHE MODE Timing without R/B#, Part 2 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 READ ID Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 PROGRAM Operation with CE# "Don't Care" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 PROGRAM PAGE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 PROGRAM PAGE Operation with RANDOM DATA INPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 INTERNAL DATA MOVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 PROGRAM PAGE CACHE MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 PROGRAM PAGE CACHE MODE Ending on 15h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 BLOCK ERASE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 RESET Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 63-Ball VFBGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48aLOF.fm - Rev. 2.0 6/06 EN 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Draft 6/ 28/ 2006 www..com Micron Confidential and Proprietary Advance 1Gb: x8, x16 NAND Flash Memory List of Tables List of Tables Table 1: Table 2: Table 3: Table 4: Table 5: Table 6: Table 7: Table 8: Table 9: Table 10: Table 11: Table 12: Table 13: Table 14: Table 15: Table 16: Table 17: Table 18: Table 19: Table 20: Table 21: Table 22: Table 23: Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Array Addressing: MT29F1G08 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Array Addressing: MT29F1G16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Operational Example (x8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Operational Example (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Command Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Device ID and Configuration Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Status Register Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Block Lock Address Cycle Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Block Lock Status Register Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 Status Register Contents After Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 I/O Drive Strength Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 Programmable I/O Drive Strength Register READ/WRITE Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Absolute Maximum Ratings by Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 DC and Operating Characteristics, VCC = 1.65V-1.95V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Valid Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 AC Characteristics - Command, Data, and Address Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 AC Characteristics - Normal Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 PROGRAM/ERASE Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48aLOT.fm - Rev. 2.0 6/06 EN 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Draft 6/ 28/ 2006 www..com Micron Confidential and Proprietary Advance 1Gb: x8, x16 NAND Flash Memory General Description General Description The MT29F1G08 and MT29F1G16 are both 1-gigabit NAND Flash memory devices. NAND Flash technology provides a cost-effective solution for applications requiring high-density, solid-state storage. The MT29F1Gxx devices include standard NAND Flash features as well as new features designed to enhance system-level performance. The MT29F1Gxx devices use a multiplexed 8- or 16-bit bus (I/O[7:0] or I/O[15:0]) to transfer data, address, and instruction information. The five control pins (CLE, ALE, CE#, RE#, WE#) implement the NAND Flash command bus interface protocol. Additional pins control hardware write protection (WP#), monitor the device ready/busy (R/B#) state, and enable BLOCK LOCK functions (LOCK). This hardware interface creates a low-pin-count device with a standard pinout that is the same from one density to another, enabling future upgrades to higher densities without any board redesign. MT29F1Gxx devices contain 1,024 erasable blocks. Each block is subdivided into 64 programmable pages. Each page consists of 2,112 bytes (x8), 1,056 words (x16). The pages are further divided into a 2,048-byte data storage region with a separate 64-byte area on the x8 device; and on the x16 device, separate 1,024-word and 32-word areas. The 64byte and 32-word areas are typically used for error correction functions. Figure 3: Functional Block Diagram: 1Gb NAND Flash VCC VSS I/O [7:0] I/O [15:0] I/O Control Address Register Status Register Command Register CE# CLE ALE WE# RE# WP# LOCK Data Register R/B# Cache Register Row Decode Control Logic Column Decode PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. 2.0 6/06 EN 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Draft 6/ 28/ 2006 On-chip control logic automates PROGRAM and ERASE operations to maximize cycle endurance. ERASE/PROGRAM endurance is specified at 100K cycles when using appropriate error correcting code (ECC) and bad-block-management software. www..com Micron Confidential and Proprietary Advance 1Gb: x8, x16 NAND Flash Memory General Description Figure 4: Ball Diagram (x8), 63-Ball VFBGA 1 2 3 4 5 6 NC NC NC NC NC NC NC A WP# ALE Vss CE# WE# R/B# B NC RE# CLE NC NC NC C NC NC NC NC NC NC D NC NC NC NC NC NC E NC NC LOCK NC NC NC F NC I/O0 NC NC NC Vcc G NC I/O1 NC Vcc I/O5 I/O7 H Vss I/O2 I/O3 I/O4 I/O6 Vss NC NC NC NC NC NC NC NC Top View, Ball Down Notes: 1. For package dimensions, see Figure 70 on page 72. PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. 2.0 6/06 EN 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Draft 6/ 28/ 2006 www..com Micron Confidential and Proprietary Advance 1Gb: x8, x16 NAND Flash Memory General Description Figure 5: Ball Diagram (x16), 63-Ball VFBGA 1 2 3 4 5 6 NC NC NC NC NC NC NC A WP# ALE Vss CE# WE# R/B# B NC RE# CLE NC NC NC C NC NC NC NC NC NC E NC NC LOCK I/O5 I/O7 NC F I/O8 I/O1 I/O10 I/O12 I/O14 Vcc G I/O0 I/O9 I/O3 Vcc I/O6 I/O15 H Vss I/O2 I/O11 I/O4 I/O13 Vss NC NC NC NC NC NC NC NC Top View, Ball Down Notes: 1. For package dimensions, see Figure 70 on page 72. PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. 2.0 6/06 EN 9 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Draft 6/ 28/ 2006 D NC NC NC NC NC NC www..com Micron Confidential and Proprietary Advance 1Gb: x8, x16 NAND Flash Memory General Description Table 1: Symbol ALE Pin Descriptions Type Input Pin Function Address latch enable: During the time ALE is HIGH, address information is transferred from I/O[7:0] into the on-chip address register. Upon a LOW to HIGH transition on WE#--when address information is not being loaded--the ALE pin should be driven LOW. Chip enable: Used to gate transfers between the host system and the NAND Flash device. Once the device becomes busy, starts a PROGRAM or ERASE operation. CE# can be de-asserted. See the Bus Operation section for additional operational details. Command latch enable: When CLE is HIGH, information is transferred from I/O [7:0] to the on-chip command register on the rising edge of WE#. When command information is not being loaded, the CLE pin should be driven LOW. When LOCK is HIGH during power-up, the BLOCK LOCK function is enabled. To disable the BLOCK LOCK, connect LOCK to VSS during power-up, or leave it unconnected (internal pull-down). Read enable: Used to gate transfers from the NAND Flash device to the host system. Write enable: Used to gate transfers from the host system to the NAND Flash device. Write protect: Used to protect against inadvertent PROGRAM and ERASE operations. All PROGRAM and ERASE operations are disabled when the WP# is LOW. Data inputs/outputs: The bi-directional I/O pins transfer address, data and instruction information. Data is output only during READ operations; at other times the I/O pins are inputs. CE# Input CLE Input LOCK Input RE# WE# WP# I/O[7:0] (x8) I/O[15:0] (x16) R/B# Input Input Input I/O Output VCC VSS NC Supply Supply - Ready/busy: The ready/busy pin is an open-drain, active-LOW output, that uses an external pull-up resistor. The pin is used to indicate when the chip is processing a PROGRAM or ERASE operation. The pin is also used during READ operations to indicate when data is being transferred from the array into the serial data register. When these operations have completed, the ready/busy pin returns to the highimpedance state. VCC: The VCC pin is the power supply pin. VSS: The VSS pin is the ground connection. No connect: NC pins are not internally connected. These pins can be driven or left unconnected. PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. 2.0 6/06 EN 10 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Draft 6/ 28/ 2006 www..com Micron Confidential and Proprietary Advance 1Gb: x8, x16 NAND Flash Memory Architecture Architecture The MT29F1G08 and MT29F1G16 use NAND Flash electrical and command interfaces. Data, commands, and addresses are multiplexed onto the same pins. This provides a memory device with low pin count. The internal memory array is accessed on a page basis. When performing reads, a page of data is copied from the memory array into the data register. Once copied to the data register, data is output sequentially, byte by byte on the x8 device, or word by word on the x16 device. The memory array is programmed on a page basis. After the starting address is loaded into the internal address register, data is sequentially written to the internal data register up to the end of a page. After all page data has been loaded into the data register, array programming is started. In order to increase programming bandwidth, this device incorporates a cache register. In the cache programming mode, data is first copied into the cache register and then into the data register. Once the data is copied into the data register, programming begins. After the data register has been loaded and programming started, the cache register becomes available for loading additional data. Loading the next page of data into the cache register takes place while page programming is in process. Addressing The MT29F1G08 and MT29F1G16 devices do not have dedicated address pins. Addresses are loaded using a four-cycle sequence as shown in Tables 2 and 3. Table 2 presents address functions internal to the MT29F1G08 device; Table 3, the MT29F1G16. See Figures 8 and 9 on pages 14 and 15 for additional memory mapping and addressing details. PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. 2.0 6/06 EN 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Draft 6/ 28/ 2006 The INTERNAL DATA MOVE command also uses the internal cache register. Normally, moving data from one area of external memory to another uses a large number of external memory cycles. By using the internal cache register and data register, array data can be copied from one page and then programmed into another without using external memory cycles. www..com Micron Confidential and Proprietary Advance 1Gb: x8, x16 NAND Flash Memory Addressing Figure 6: Array Organization for MT29F1G08 (x8) 2,112 bytes I/O 0 Cache Register Data Register 2,048 2,048 64 64 I/O 7 1 page 1 block 1,024 blocks per device = (2K + 64 bytes) = (2K + 64) bytes x 64 pages = (128K + 4K) bytes 1 Block 1 device = (2K + 64) bytes x 64 pages x 1,024 blocks = 1,056 Mbits Table 2: Cycle First Second Third Fourth Array Addressing: MT29F1G08 I/O7 CA7 LOW BA19 BA27 I/O6 CA6 LOW BA18 BA26 I/O5 CA5 LOW PA17 BA25 I/O4 CA4 LOW PA16 BA24 I/O3 CA3 CA11 PA15 BA23 I/O2 CA2 CA10 PA14 BA22 I/O1 CA1 CA9 PA13 BA21 I/O0 CA0 CA8 PA12 BA20 Notes: 1. Block address concatenated with page address = actual page address. CAx = column address; PAx = page address; BAx = block address. 2. Note that the 12-bit column address is capable of addressing from 0 to 4,095 bytes on a x8 device; however, only bytes 0 through 2,111 are valid. Bytes 2,112 through 4,095 of each page are "out of bounds," do not exist in the device, and cannot be addressed. PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. 2.0 6/06 EN 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Draft 6/ 28/ 2006 www..com Micron Confidential and Proprietary Advance 1Gb: x8, x16 NAND Flash Memory Addressing Figure 7: Array Organization for MT29F1G16 (x16) 1,056 words I/O 0 Cache Register Data Register 1,024 1,024 32 32 I/O 15 1 page 1 block 1,024 blocks per device = (1K + 32) words = (1K + 32) words x 64 pages = (64K + 2K) words 1 Block 1 device = (1K + 32) words x 64 pages x 1,024 blocks = 1,056 Mbits Table 3: Cycle First Second Third Fourth Array Addressing: MT29F1G16 I/O[15:8] LOW LOW LOW LOW I/O7 CA7 LOW BA18 BA26 I/O6 CA6 LOW BA17 BA25 I/O5 CA5 LOW PA16 BA24 I/O4 CA4 LOW PA15 BA23 I/O3 CA3 LOW PA14 BA22 I/O2 CA2 CA10 PA13 BA21 I/O1 CA1 CA9 PA12 BA20 I/O0 CA0 CA8 PA11 BA19 Notes: 1. Block address concatenated with page address = actual page address. CAx = column address; PAx = page address; BAx = block address. 2. I/O[15:8] are not used during addressing sequence and should be driven LOW. 3. Note that the 12-bit column address is capable of addressing from 0 to 4,095 bytes on a x8 device; however, only bytes 0 through 2,111 are valid. Bytes 2,112 through 4,095 of each page are "out of bounds," do not exist in the device, and cannot be addressed. PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. 2.0 6/06 EN 13 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Draft 6/ 28/ 2006 www..com Micron Confidential and Proprietary Advance 1Gb: x8, x16 NAND Flash Memory Addressing Memory Mapping Figure 8: Memory Map x8 0 1 2 * * * * * * * * * * * * 1,023 Blocks BA[27:18] Pages PA[17:12] 0 1 2 *** 63 Bytes CA[11:0] 0 1 2 ******************* 2,047 *** 2,111 Spare area Table 4: Block 0 0 0 ... 1,023 1,023 Operational Example (x8) Page 0 1 2 ... 62 63 Min Address in Page 0x00000000 0x00010000 0x00020000 ... 0xFFFE0000 0xFFFF0000 Max Address in Page 0x0000083F 0x0000183F 0x0000283F ... 0xFFFE083F 0xFFFF083F Out of Bounds Addresses in Page 0x00000840-0x00000FFF 0x00010840-0x00010FFF 0x00020840-0x00020FFF 0xFFFE0840-0xFFFE0FFF 0xFFFF0840-0xFFFF0FFF Notes: 1. As shown in Table 2 on page 12, the high 4 bits of the second ADDRESS cycle have no assigned address bits. However, these 4 bits must be held LOW during the ADDRESS cycle to ensure that the address is interpreted correctly by the NAND Flash device. These extra bits are accounted for in the second ADDRESS cycle even though they have no address bits assigned to them. 2. Note that the 12-bit column address is capable of addressing from 0 to 4,095 bytes on a x8 device; however, only bytes 0 through 2,111 are valid. Bytes 2,112 through 4,095 of each page are "out of bounds," do not exist in the device, and cannot be addressed. PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. 2.0 6/06 EN 14 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Draft 6/ 28/ 2006 www..com Micron Confidential and Proprietary Advance 1Gb: x8, x16 NAND Flash Memory Addressing Figure 9: Memory Map x16 0 1 2 * * * * * * * * * * * * 1,023 Blocks BA[26:17] Pages PA[16:11] 0 1 2 *** 63 Words CA[10:0] 0 1 2 ******************* 1,023 *** 1,055 Spare area Table 5: Block 0 0 0 ... 1,023 1,023 Operational Example (x16) Page 0 1 2 ... 62 63 Min Address in Page 0x00000000 0x00010000 0x00020000 ... 0xFFFE0000 0xFFFF0000 Max Address in Page 0x0000041F 0x0001041F 0x0002041F ... 0xFFFE041F 0xFFFF041F Out of Bounds Addresses in Page 0x00000420-0x00000FFF 0x00010420-0x00010FFF 0x00020420-0x00020FFF 0xFFFE0420-0x00020FFF 0xFFFF0420-0xFFFF0FFF Notes: 1. As shown in Table 3 on page 13, the high 5 bits of ADDRESS cycle 2 have no assigned address bits. However, these 5 bits must be held LOW during the ADDRESS cycle to ensure that the address is interpreted correctly by the NAND Flash device. These extra bits are accounted for in ADDRESS cycle 2 even though they have no address bits assigned to them. 2. Note that the 11-bit column address is capable of addressing from 0 to 2,047 words on a x16 device; however, only words 0 through 1,055 are valid. Words 1,056 through 2,047 of each page are "out of bounds," do not exist in the device, and cannot be addressed. PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. 2.0 6/06 EN 15 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Draft 6/ 28/ 2006 www..com Micron Confidential and Proprietary Advance 1Gb: x8, x16 NAND Flash Memory Bus Operation Bus Operation The bus on the MT29F1Gxx devices is multiplexed. Data I/O, addresses and commands all share the same pins. I/O pins I/O[15:8] are used only for data in the x16 configuration. Addresses and commands are always supplied on I/O[7:0]. The command sequence normally consists of a COMMAND LATCH cycle, ADDRESS LATCH cycle and a DATA cycle--either READ or WRITE. Control Signals CE#, WE#, RE#, CLE, ALE and WP control NAND Flash-device READ and WRITE operations. CE# is used to enable the device. When CE# is LOW and the device is not in the BUSY state, the NAND Flash memory will accept command, data, and address information. When the device is not performing an operation, the CE# pin is typically driven HIGH and the device enters standby mode. The memory will enter standby if CE# goes HIGH while data is being transferred and the device is not busy. This helps reduce power consumption (see Figure 62 on page 67). The CE# "Don't Care" operation enables the NAND Flash to reside on the same asynchronous memory bus as other Flash or SRAM devices. Other devices on the memory bus can then be accessed while the NAND Flash is busy with internal operations. This capability is important for designs that require multiple NAND Flash devices on the same bus. One device can be programmed while another is being read. A HIGH CLE signal indicates that a COMMAND cycle is taking place. A HIGH ALE signal signifies that an ADDRESS INPUT cycle is occurring. Commands Commands are written to the command register on the rising edge of WE# when: * CE# and ALE are LOW, and * CLE is HIGH, and * the device is not busy. The READ STATUS and RESET commands are different because they can be written to the device while it is busy. Commands are transferred to the command register on the rising edge of WE# (see Figure 30 on page 37. Commands are input on I/O[7:0] only. For devices with a x16 interface, I/O[15:8] must be written with zeros when issuing a command. Address Input Addresses are written to the address register on the rising edge of WE# when: * CE# and CLE are LOW, and * ALE is HIGH. Addresses are input on I/O[7:0] only. For devices with a x16 interface, I/O[15:8] must be written with zeros when issuing an address. Generally all four ADDRESS cycles are written to the device. An exception to this is the BLOCK ERASE command, which requires only two ADDRESS cycles. See the "BLOCK ERASE Operation" section on page 33 for details. RANDOM DATA INPUT and OUTPUT commands need only column addresses, so only two ADDRESS cycles are required. Refer to the command descriptions to determine the addressing requirements for each command. PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. 2.0 6/06 EN 16 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Draft 6/ 28/ 2006 www..com Micron Confidential and Proprietary Advance 1Gb: x8, x16 NAND Flash Memory Bus Operation Data Input Data is written to the data register on the rising edge of WE# when: * CE#, CLE, and ALE are LOW, and * the device is not busy. Data is input on I/O[7:0] for x8 devices, and I/O[15:0] on x16 devices. See Figure 50 on page 59 for additional data input details. READs After a READ command is issued, data is transferred from the memory array to the data register on the rising edge of WE#. R/B# goes LOW for tR and transitions HIGH after the transfer is complete. When data is available in the data register, it is clocked out of the part by RE# going LOW. See Figure 16 on page 22 for timing details. The READ STATUS (70h) command or the READY/BUSY signal can be used to determine when the device is ready. See the READ STATUS command section starting on page 29 for details. READY/BUSY# The combination of Rp and capacitive loading of the R/B# circuit determine the rise time of the R/B# pin. The actual value used for Rp depends on the system timing requirements. Large values of Rp cause R/B# to be delayed significantly. At the 10 percent/90 percent points on the R/B# waveform, rise time is approximately two time constants (TC). Figure 10: Time Constants TC = R x C where R = Rp and C = Total capacitive load The fall time of the R/B# signal is determined mainly by the output impedance of the R/B# pin and the total load capacitance. Refer to Figure 13 on page 18, and Figure 14 on page 19, which depict approximate Rp values using a circuit load of 100pF. The minimum value for Rp is determined by the output drive capability of the R/B# signal, the output voltage swing, and VCC. Figure 11: Minimum Rp Rp (MIN, 1.8V part) = VCC (MAX) - VOL (MAX) IOL + IL = 1.85V 3mA + IL where IL is the sum of the input currents of all devices tied to the R/B# pin PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. 2.0 6/06 EN 17 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Draft 6/ 28/ 2006 The R/B# output provides a hardware method of indicating the completion of a PROGRAM/ERASE/READ operation. The signal is typically HIGH, and transitions to LOW after the appropriate command is written to the device. The signal pin's open-drain driver enables multiple R/B# outputs to be OR-tied. The signal requires a pull-up resistor for proper operation. The READ STATUS command can be used in place of R/B#. Typically, R/B# would be connected to an interrupt pin on the system controller (See Figure 12 on page 18). www..com Micron Confidential and Proprietary Advance 1Gb: x8, x16 NAND Flash Memory Bus Operation Figure 12: READY/BUSY# Open Drain Rp VCC R/B# Open drain output IOL GND Device Figure 13: t Fall and tRise 3.50 3.00 2.50 2.00 V tFall tRise 1.50 1.00 0.50 0.00 -1 0 2 4 TC 0 2 4 6 VCC 1.8 Notes: 1. 2. 3. 4. tFall and tRise are calculated at 10 percent and 90 percent points. is primarily dependent on external pull-up resistor and external capacitive loading. tFall 7ns at 1.8V. See TC values in Figure 15 on page 19 for approximate Rp value and TC. tRise PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. 2.0 6/06 EN 18 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Draft 6/ 28/ 2006 www..com Micron Confidential and Proprietary Advance 1Gb: x8, x16 NAND Flash Memory Bus Operation Figure 14: IOL vs. Rp 3.50mA 3.00mA 2.50mA 2.00mA I 1.50mA 1.00mA 0.50mA 0.00mA 0 2,000 4,000 6,000 Rp 8,000 10,000 12,000 IOL at 1.95V (MAX) Note: To calculate Rp value, see Figure 11, Minimum Rp, on page 17. 1.20s 1.00s 800ns T 600ns 400ns 200ns 0ns 0 2k 4k 6k 8k 10k 12k Rp IOL at 1.95V (MAX) RC = TC C = 100pf PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. 2.0 6/06 EN 19 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Draft 6/ 28/ 2006 Figure 15: TC vs. Rp www..com Micron Confidential and Proprietary Advance 1Gb: x8, x16 NAND Flash Memory Bus Operation Table 6: CLE H L H L L L L X X X X Mode Selection ALE L H L H L L L X X X X CE# L L L L L L L X X X H H H X X X X H X X X X WE# RE# H H H H H WP# X X H H H X X H H L 0V/VCC2 Data input Sequential read and data output During READ (busy) During PROGRAM (busy) During ERASE (busy) Write protect Standby Write mode Mode Read mode Command input Address input Command input Address input Notes: 1. Mode selection settings for this table: H = Logic level HIGH L = Logic level LOW X = VIH or VIL 2. WP# should be biased to CMOS HIGH or LOW for standby. PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. 2.0 6/06 EN 20 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Draft 6/ 28/ 2006 www..com Micron Confidential and Proprietary Advance 1Gb: x8, x16 NAND Flash Memory Command Definitions Command Definitions Table 7: Command BLOCK ERASE BLOCK LOCK BLOCK LOCK READ STATUS BLOCK LOCK TIGHT BLOCK UNLOCK OTP DATA PROGRAM OTP DATA PROTECT OTP DATA READ PAGE READ PAGE READ CACHE MODE START PAGE READ CACHE MODE LAST PROGRAM for INTERNAL DATA MOVE PROGRAM PAGE PROGRAM PAGE CACHE PROGRAMMABLE DRIVE STRENGTH RANDOM DATA INPUT for PROGRAM RANDOM DATA READ READ for INTERNAL DATA MOVE READ ID READ ID (ONFI) READ PARAMETER PAGE (ONFI) READ STATUS RESET Command Set First Cycle 60h 2Ah 7Ah 2Ch 23h-24h A0h A5h AFh 00h 31h 3Fh 85h 80h 80h B8h 85h 05h 00h 90h 90h ECh 70h FFh Second Cycle D0h - - - - 10h 10h 30h 30h - - 10h 10h 15h - - E0h 35h - - - - - Valid During Busy No No No No No No No No No No No No No No No No No No No No No Yes Yes Notes 2 1 Notes: 1. RANDOM DATA READ command is limited to use within a single page. 2. RANDOM DATA INPUT for PROGRAM command is limited to use within a single page. PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. 2.0 6/06 EN 21 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Draft 6/ 28/ 2006 www..com Micron Confidential and Proprietary Advance 1Gb: x8, x16 NAND Flash Memory Command Definitions READ Operations PAGE READ 00h-30h To enter READ mode, write a 00h command to the device, then specify the starting address via the ADDRESS cycles, and finally issue the 30h command. At this point the device enters a busy state while it fetches data from the NAND Flash array. During this time, the ready/busy status of the device can be monitored using the R/B# pin or the READ STATUS (70h) command. The R/B# signal is LOW when the device is busy fetching data from the NAND Flash array. When R/B# returns to HIGH, data is ready for output. Pulsing the RE# line results in data output on the I/O lines. Note that the first byte or word of data output is that which was specified in the ADDRESS cycle. Each pulse of the RE# signal increases the address counter by one so additional address cycles are not required when reading sequential data. If the system does not have a R/B# signal, the NAND Flash device status can be monitored by issuing a READ STATUS (70h) command, then reading bit 5 or 6 from the status register (0 = busy, 1 = ready). If the READ STATUS command is used to monitor the data transfer, the user must re-issue the READ (00h) command to initiate data output from the data register. The user can issue 00h only after R/B# goes HIGH or the status register value is E0h. See Figure 59 on page 65 and Figure 60 on page 66 for examples. Figure 16: CLE PAGE READ Operation CE# WE# ALE tR R/B# RE# I/Ox 00h Address (4 Cycles) 30h Data Output (Serial Access) Don`t Care PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. 2.0 6/06 EN 22 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Draft 6/ 28/ 2006 www..com Micron Confidential and Proprietary Advance 1Gb: x8, x16 NAND Flash Memory Command Definitions RANDOM READ 05h-E0h The RANDOM READ command enables the user to specify a new column address so the data at single or multiple addresses can be read. The random read mode is enabled after a normal PAGE READ (00h-30h sequence). Random data can be output after the initial PAGE READ by writing an 05h-E0h command sequence along with the new column address (two cycles). The RANDOM READ command can be issued without limit within the page. Only data on the current page can be read. Pulsing the RE# pin outputs data, the same as a serial PAGE READ (see Figure 17). Figure 17: RANDOM DATA READ Operation tR R/B# RE# I/Ox 00h Address (4 Cycles) 30h Data Output 05h Address (2 Cycles) E0h Data Output PAGE READ CACHE MODE START 31h; PAGE READ CACHE MODE START LAST 3Fh Micron NAND Flash devices have a cache register that can be used to increase READ operation speed when accessing sequential pages in a block. First, a normal PAGE READ (00h-30h) command sequence is issued. See Figure 18 on page 24 for details. The R/B# signal goes LOW for tR during the time it takes to transfer the first page of data from the memory to the data register. After R/B# returns to HIGH, the PAGE READ CACHE MODE START (31h) command is latched into the command register. R/B# goes LOW for tDCBSYR1 while data is being transferred from the data register to the cache register. When the data register contents are transferred to the cache register, another PAGE READ is automatically started as part of the 31h command. Data is transferred from the memory array to the data register at the same time data is being output (pulsing of RE#) from the cache register. If the total time to output data exceeds tR, then the PAGE READ is hidden. The second and subsequent pages of data are transferred to the cache register by issuing additional 31h commands. R/B# will stay LOW up to tDCBSYR2. This time can vary, depending on whether the previous memory-to-data-register transfer was completed prior to issuing the next 31h command. If the data transfer from memory to the data register is not completed before the 31h command is given, R/B# stays LOW until the transfer is complete. It is not necessary to output a whole page of data before issuing another 31h command. R/B# will stay LOW until the previous PAGE READ is complete and the data has been transferred to the cache register. To read out the last page of data, the PAGE READ CACHE MODE START LAST (3Fh) command is issued. This command transfers data from the data register to the cache register without another PAGE READ. See Figure 18 on page 24 for details. PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. 2.0 6/06 EN 23 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Draft 6/ 28/ 2006 www..com Micron Confidential and Proprietary Advance 1Gb: x8, x16 NAND Flash Memory Command Definitions tDCBSYR2 Data Output (Serial Access) 3fh Data Output (Serial Access) Don`t Care PAGE READ CACHE MODE tR Figure 18: CLE ALE PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. 2.0 6/06 EN WE# R/B# I/Ox CE# RE# 00h Address (4 Cycles) 30h 24 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Draft 6/ 28/ 2006 31h Data Output (Serial Access) 31h tDCBSYR1 tDCBSYR2 www..com Micron Confidential and Proprietary Advance 1Gb: x8, x16 NAND Flash Memory Command Definitions READ ID 90h The READ ID command is used to read the identifier codes from the MT29F1G08 and MT29F1G16 devices. The READ ID command reads a 5-byte table that includes the manufacturer ID, device configuration, and part-specific information. See Table 8 on page 26, which shows a complete listing of configuration details. Issuing a 90h command to the command register and a 00h command to the address register puts the device in read ID mode. The device will remain in this mode until another valid command and address are issued (see Figure 19). If a 90h command is issued without an address, the device will remain in read ID mode. Figure 19: CLE READ ID Operation CE# WE# tAR ALE RE# tWHR tREA I/Ox 90h 00h Address, 1 Cycle Byte 0 Manufacturer ID 1 Byte 1 Device ID 1 Byte 2 Byte 31 Byte 4 Notes: 1. See Table 8 on page 26 for byte definitions. PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. 2.0 6/06 EN 25 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Draft 6/ 28/ 2006 www..com Micron Confidential and Proprietary Advance 1Gb: x8, x16 NAND Flash Memory Command Definitions Table 8: Device ID and Configuration Codes Options Byte 0 Byte 1 MT29F1G08ABB MT29F1G16ABB Byte 2 Number of die Cell type Number of simultaneously programmed pages Interleaved program between multiple die Cache programming Byte value MT29F1GxxABB Byte 3 Page size Spare area size (bytes) Block size (w/o spare) Organization Serial access (MIN) Byte value MT29F1G08ABB MT29F1G16ABB Byte 4 Reserved Planes per die Plane size Reserved Byte value MT29F1GxxABB Manufacturer ID Micron Device ID 1Gb, x8, 1.8V 1Gb, x16, 1.8V 1 SLC 1 Not supported (1Gb) Supported 0 1 1 I/O7 0 1 1 I/O6 0 0 0 I/O5 1 1 1 I/O4 0 0 1 I/O3 1 0 0 I/O2 1 0 0 I/O1 0 0 0 0 0 0 0 0 I/O0 0 1 1 0 Value1 Notes 2Ch A1h B1h 00b 00b 00b 0b 1b 80h 01b 01b 01b 0b 1b 0xxx0b 95h D5h 00b 00b 000b 0b 00h 0 0 0 0 0 0 0 0 1 1 0 0 1 0 1 1 0 1 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 1 1 1Gb 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Notes: 1. b = binary; h = hex. PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. 2.0 6/06 EN 26 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Draft 6/ 28/ 2006 2KB 64 128K x8 x16 50ns x8 x16 www..com Micron Confidential and Proprietary Advance 1Gb: x8, x16 NAND Flash Memory Command Definitions ONFI READ ID The ONFI READ ID function identifies that the device supports the ONFI specification. If the device supports the ONFI specification, then the ONFI signature will be returned. The ONFI signature is the ASCII encoding of "ONFI" where "O" = 4Fh, "N" = 4Eh, "F" = 46h, and "I" = 49h. Reading beyond four values yields indeterminate values. Figure 20 defines the ONFI READ ID behavior and timings. Issuing a 90h command to the command register and a 20h command to the address register puts the device into ONFI read ID mode. The device will remain in this mode until another valid command and address are issued. If a 90h command is issued without an address, the device will remain in the ONFI read ID mode. Figure 20: CLE ONFI READ ID Operation WE# ALE RE# I/O0-7 90h 20h 4Fh 4Eh 46h 49h ONFI READ PARAMETER PAGE Operation The READ PARAMETER PAGE function retrieves the data structure that describes the device's organization, features, timings, and other behavioral parameters. Figure 21 defines the READ PARAMETER PAGE behavior. Figure 21: CLE ONFI READ PARAMETER PAGE Operation WE# ALE RE# I/O0-7 ECh 00h tR I/O0-7 P0 P1 ... P1022 P1023 R/B# PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. 2.0 6/06 EN 27 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Draft 6/ 28/ 2006 www..com Micron Confidential and Proprietary Advance 1Gb: x8, x16 NAND Flash Memory Command Definitions Parameter Page Data Structure Definition For parameters that span multiple bytes, the least significant byte of the parameter corresponds to the first byte. For example, if bytes 8-9 contain a 16-bit parameter, then bits 7:0 are contained in byte 8. PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. 2.0 6/06 EN 28 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Draft 6/ 28/ 2006 www..com Micron Confidential and Proprietary Advance 1Gb: x8, x16 NAND Flash Memory Command Definitions READ STATUS 70h The MT29F1G08 and MT29F1G16 devices have an 8-bit status register that the software can read during device operation. On the x16 device I/O[15:8] are "0" when reading the status register. Table 9 describes the status register. After a READ STATUS (70h) command, all READ cycles will be from the status register until a new command is issued. Changes in the status register will be seen on 1/O[7:0] as long as CE# and RE# are LOW. It is not necessary to start a new READ cycle to see these changes. During monitoring of the status register to determine when the tR (transfer from NAND Flash array to data register) is complete, the READ (00h) command must be re-issued to make the change from STATUS READs to DATA READs. After the READ command has been re-issued, pulsing the RE# line will result in outputting data, starting from the specified column address. Table 9: SR Bit 0 1 2 3 4 5 6 7 [15:8] Status Register Bit Definition Program Page Pass/fail - Program Page Cache Mode Pass/fail (N) Pass/fail (N - 1) - - - Ready/busy Ready/busy cache Write protect - Page Read - Page Read Cache Mode - Block Erase Pass/fail Definition Notes - - - Ready/busy Ready/busy Write protect - "0" = Successful PROGRAM/ERASE "1" = Error in PROGRAM/ERASE - - - "0" = Successful PROGRAM "1" = Error in PROGRAM - - - "0" - - - "0" - - - "0" Ready/busy Ready/busy Ready/busy "0" = Busy "1" = Ready Ready/busy Ready/busy Ready/busy "0" = Busy cache "1" = Ready Write Write protect Write "0" = Protected protect protect "1" = Not protected - - - "0" 1 2 3 Notes: 1. Status register bit 5 is "0" during the actual programming operation. If cache mode is used, this bit will be "1" when all internal operations are complete. 2. Status register bit 6 is "1" when the cache is ready to accept new data. R/B# follows bit 6. See Figure 23 on page 31, and Figure 29 on page 36. 3. Status register bit 7 typically mirrors the status of the WP# pin. However, when BLOCK LOCK is used, status register bit 7 returns "0" if PROGRAM or ERASE operations are performed on a locked block. Additionally, when using the OTP PROGRAM DATA command, status register bit 7 returns "0" if the page is protected. This bit is not modified until the next PROGRAM or ERASE command is issued. PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. 2.0 6/06 EN 29 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Draft 6/ 28/ 2006 www..com Micron Confidential and Proprietary Advance 1Gb: x8, x16 NAND Flash Memory Command Definitions Figure 22: CE# tCLR Status Register Operation CLE WE# tREA RE# I/Ox 70h Status Status Status Toggle RE# as required PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. 2.0 6/06 EN 30 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Draft 6/ 28/ 2006 www..com Micron Confidential and Proprietary Advance 1Gb: x8, x16 NAND Flash Memory Command Definitions PROGRAM Operations PROGRAM PAGE 80h-10h Micron NAND Flash devices are inherently page-programmed devices. Pages must be programmed consecutively within a block, from the least significant page address to most significant page address (that is, 0, 1, 2, ..., 63). Random page address programming is prohibited. Micron NAND Flash devices also support partial-page programming operations. This means that any single bit can only be programmed one time before an erase is required; however, the page can be partitioned such that a maximum of eight programming operations are supported before an erase is required. SERIAL DATA INPUT 80h PROGRAM PAGE operations require loading the SERIAL DATA INPUT (80h) command into the command register, followed by the ADDRESS cycles, then the data. Serial data is loaded on consecutive WE# cycles starting at the given address. The PROGRAM (10h) command is written after the data input is complete. The internal control logic automatically executes the proper algorithm and controls all the necessary timing to program and verify the operation. Write verification only detects "1s" that are not successfully written to "0s." R/B# goes LOW for the duration of array programming time, tPROG. The READ STATUS REGISTER (70h) command and the RESET (FFh) command are the only commands valid during the programming operation. Bit 6 of the status register will reflect the state of R/B#. Once the device reaches ready, read bit 0 of the status register to determine if the program operation passed or failed. See Figure 23 for details. The command register stays in read status register mode until another valid command is written to it. RANDOM DATA INPUT 85h After the initial data set is input, additional data can be written to a new column address with the RANDOM DATA INPUT (85h) command. The RANDOM DATA INPUT command can be used any number of times in the same page prior to issuing the PAGE WRITE (10h) command. See Figure 24 on page 31 for the proper command sequence. Figure 23: PROGRAM and READ STATUS Operation tPROG R/B# 70h I/Ox 80h Address DIN 10h Status Figure 24: RANDOM DATA INPUT tPROG R/B# I/Ox 80h Address DIN 85h Address (2 Cycles) DIN 10h 70h Status PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. 2.0 6/06 EN 31 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Draft 6/ 28/ 2006 www..com Micron Confidential and Proprietary Advance 1Gb: x8, x16 NAND Flash Memory Command Definitions PROGRAM PAGE CACHE MODE 80h-15h Cache programming is actually a buffered programming mode of the standard page programming command. Programming is started by loading the SERIAL DATA INPUT (80h) command to the command register, followed by four cycles of address, and a full or partial page of data. The data is initially copied into the cache register, and the CACHE WRITE (15h) command is then latched to the command register. Data is transferred from the cache register to the data register on the rising edge of WE#. R/B# goes LOW during this transfer time. After the data has been copied into the data register and R/B# returns to HIGH, memory array programming begins. When R/B# returns to HIGH, new data can be written to the cache register by issuing another CACHE PROGRAM command sequence. The time that R/B# stays LOW will be controlled by the actual programming time. The first time through equals the time it takes to transfer the cache register contents to the data register. On the second and subsequent programming passes, transfer from the cache register to the data register is held off until current data register content has been programmed into the array. Bit 6 (cache R/B#) of the status register can be read by issuing the READ STATUS (70h) command to determine when the cache register is ready to accept new data. The R/B# pin always follows bit 6. If just the R/B# pin is used to determine programming completion, the last page of the program sequence must use the PROGRAM PAGE (10h) command instead of the CACHE PROGRAM (15h) command. If the CACHE PROGRAM (15h) command is used every time, including the last page of the programming sequence, status register bit 5 must be used to determine when programming is complete. Pass/fail status is in two steps: bit 1 returns the pass/fail state of the previous page when R/B# returns to HIGH. Bit 0 of the status register returns the pass/fail for the previous page when bit 6 of the status register is a "1" (ready state). The pass/fail status of the current programming operation is returned with bit 0 of the status register when bit 5 of the status register is a "1" (ready state) (see Figure 25). Figure 25: R/B# PROGRAM PAGE CACHE MODE Example tCBSY tCBSY tCBSY tLPROG1 I/Ox 80h Address & Data Input 15h 80h Address & Data Input 15h 80h Address & Data Input 15h 80h Address & Data Input 10h A: Without status reads tCBSY tPROG R/B# Status2 Output Status1 Output I/Ox 80h Address & Data Input 15h 70h 80h Address & Data Input 10h 70h B: With status reads Notes: 1. For definition of tLPROG, see Table 23 on page 57, Note 3. 2. Check I/O[6:5] for internal ready/busy. Check I/O[1:0] for pass/fail. RE# can stay LOW or pulse multiple times after a 70h command. PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. 2.0 6/06 EN 32 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Draft 6/ 28/ 2006 Bit 5 (R/B#) of the status register can be polled to determine when the actual programming of the array is complete for the current programming cycle. www..com Micron Confidential and Proprietary Advance 1Gb: x8, x16 NAND Flash Memory Command Definitions INTERNAL DATA MOVE Operations An internal data move requires two command sequences. Issue a READ for INTERNAL DATA MOVE (00h-35h) command first, then the INTERNAL DATA MOVE (85h-10h) command. Data moves are only supported within the die from which data is read. READ FOR INTERNAL DATA MOVE 00h-35h This READ command is used in conjunction with the INTERNAL DATA MOVE (85h-10h) command. First, 00h is written to the command register, then the internal source address is written (4 cycles). After the address is input, the READ for INTERNAL DATA MOVE (35h) command writes to the command register. This transfers a page from memory into the cache register. The written column addresses are ignored even though all four ADDRESS cycles are required. The memory device is now ready to accept the INTERNAL DATA MOVE (85h-10h) command. Please refer to the description of this command in the following section. INTERNAL DATA MOVE 85h-10h After the READ for INTERNAL DATA MOVE command has been issued and R/B# goes HIGH, the INTERNAL DATA MOVE command can be written to the command register. This command transfers the data from the cache register to the data register and programming of the new destination page begins. After the INTERNAL DATA MOVE command and address sequence are written to the device, R/B# goes LOW while the internal control logic automatically programs the new page. The READ STATUS command and bit 6 of the status register can be used instead of the R/B# line to determine when the WRITE is complete. Bit 0 of the status register indicates if the operation was successful. The RANDOM DATA INPUT (85h) command can be used during the INTERNAL DATA MOVE command sequence to modify a word or multiple words of the original data. First, data is copied into the cache register using the 00h-35h command sequence, then the RANDOM DATA INPUT (85h) command is written, along with the address of the data to be modified next. New data is input on the external data pins. This copies the new data into the cache register. When 10h is written to the command register, the original data plus the modified data are transferred to the data register, and programming of the new page is started. The RANDOM DATA INPUT command can be issued as many times as necessary before starting the programming sequence with 10h. See Figures 26 and 27 on page 34 for details. Because the INTERNAL DATA MOVE operation does not utilize external memory, ECC cannot be used to check for errors before programming the data to a new page. This can lead to a data error if the source page contains a bit error due to charge loss or charge gain. In the case that multiple INTERNAL DATA MOVE operations are performed, these bit errors may accumulate without correction. For this reason, it is highly recommended that systems utilizing the INTERNAL DATA MOVE operation use a robust ECC scheme that can correct two or more bits per sector. PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. 2.0 6/06 EN 33 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Draft 6/ 28/ 2006 www..com Micron Confidential and Proprietary Advance 1Gb: x8, x16 NAND Flash Memory Command Definitions Figure 26: INTERNAL DATA MOVE tR tPROG R/B# I/Ox 00h Address 35h 85h Address 10h 70h Status Figure 27: INTERNAL DATA MOVE with RANDOM DATA INPUT tR tPROG R/B# I/Ox 00h Address 35h 85h Address Data 85h Address (2 Cycles) Data 10h 70h Unlimited number of repetitions. BLOCK ERASE 60h-D0h Erasing occurs at the block level. The MT29F1G08 and the MT29F1G16 have 1,024 erase blocks organized as 64 pages per block. The BLOCK ERASE command operates on one block at a time (see Figure 28). Two cycles of addresses A[27:18] are required for the x8 device, and two cycles of A[26:17] for the x16 device. Although addresses A[17:12] (x8) and A[16:11] (x16) are loaded, they are a "Don't Care" and are ignored for BLOCK ERASE operations. See Figures 8 and 9 on pages 14 and 15 for addressing details. The actual BLOCK ERASE command sequence is a two-step process. First, write the ERASE SETUP (60h) command to the command register. Then write 2 cycles of addresses to the device. Next, write the ERASE CONFIRM (D0h) command to the command register. At the rising edge of WE#, R/B# goes LOW and the internal control logic automatically controls the timing and erase-verify operations. R/B# stays LOW for the entire tBERS erase time. The READ STATUS REGISTER command can be used to check the status of the ERASE operation. When bit 6 = "1," the ERASE operation is complete. Bit 0 indicates a pass/fail condition where "0" = pass. See BLOCK ERASE, and Table 9 on page 29 for details. Figure 28: BLOCK ERASE Operation tBERS R/B# I/Ox 60h Address D0h 70h Status PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. 2.0 6/06 EN 34 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Draft 6/ 28/ 2006 www..com Micron Confidential and Proprietary Advance 1Gb: x8, x16 NAND Flash Memory Command Definitions One-Time Programmable (OTP) Area This Micron NAND Flash device offers a protected, one-time programmable NAND Flash memory area. Ten full pages (2,112 bytes or 1,056 words per page) of OTP data is available on the device, and the entire range is guaranteed to be good. The OTP area is accessible only through the OTP commands. Customers can use the OTP area in any way they desire; typical uses include programming serial numbers or other data for permanent storage. In Micron NAND Flash devices, the OTP area leaves the factory in a non-written state (all bits are "1s"). Programming or partial-page programming enables the user to program only "0" bits in the OTP area. The OTP area cannot be erased, even if it is not protected. Protecting the OTP area simply prevents further programming of the OTP area. While the OTP area is referred to as "one-time programmable," Micron provides a unique way to program and verify data--before permanently protecting it and preventing future changes. OTP programming and protection are accomplished in two discrete operations. First, using the OTP DATA PROGRAM (A0h-10h) command, an OTP page is programmed entirely in one operation, or in up to four partial-page programming sequences. Programming can occur on other pages within the OTP area in a similar manner. Second, the OTP area is permanently protected from further programming using the OTP DATA PROTECT (A5h-10h) command. The pages within OTP area can always be read using the OTP DATA READ (AFh-30h) command, whether or not it is protected. OTP DATA PROGRAM A0h-10h The OTP DATA PROGRAM (A0h-10h) command is used to write data to the pages within the OTP area. An entire page can be programmed at one time, or a page can be partially programmed up to four times. There is no ERASE operation for the OTP pages. The OTP DATA PROGRAM enables programming into an offset of an OTP page, using the two bytes of column address (CA[11:0]). The OTP DATA PROGRAM command will not execute if the OTP area has been protected. To use the OTP DATA PROGRAM command, issue the A0h command. Issue four ADDRESS cycles: the first two ADDRESS cycles are the column address, and for the remaining two cycles select a page in the range of 02h-0Bh. Next, write the data: from 1 to 2,112 bytes (x8 device), or from 1 to 1,056 words (x16 device). After data input is complete, issue the 10h command. The internal control logic automatically executes the proper programming algorithm and controls the necessary timing for programming and verification. Program verification only detects "1s" that are not successfully written to "0s." RANDOM DATA INPUT (05h-E0h)commands are supported during OTP DATA PROGRAM operations. R/B# goes LOW during the duration of the array programming time (tPROG). The READ STATUS (70h) command is the only command valid during the OTP DATA PROGRAM operation. Bit 5 of the status register will reflect the state of R/B#. If bit 7 is "0," then the OTP area has been protected; otherwise, it will be a "1." When the device is ready, read bit 0 of the status register to determine if the operation passed or failed (see Table 9 on page 29). PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. 2.0 6/06 EN 35 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Draft 6/ 28/ 2006 www..com Micron Confidential and Proprietary Advance 1Gb: x8, x16 NAND Flash Memory Command Definitions Figure 29: CLE OTP DATA PROGRAM CE# tWC WE# tWB tPROG ALE RE# I/Ox A0h OTP DATA INPUT Command Col Add 1 Col Add 2 OTP Page1 00h DIN N DIN M 10h PROGRAM Command 70h READ STATUS Command Status R/B# x8 device: m = 2,112 bytes x16 device: m = 1,056 words OTP Data Written (following "good" status confirmation) Don't Care Notes: 1. The OTP page must be within the range 02h-0Bh. PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. 2.0 6/06 EN 36 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Draft 6/ 28/ 2006 OTP Address1 1 up to m bytes Serial Input www..com Micron Confidential and Proprietary Advance 1Gb: x8, x16 NAND Flash Memory Command Definitions OTP DATA PROTECT A5h-10h The OTP DATA PROTECT (A5h-10h) command is used to protect all the data in the OTP area. After the data is protected it cannot be programmed further. When the OTP area is protected, the pages within the area are no longer programmable and cannot be unprotected. To use the OTP DATA PROTECT command, issue the A5h command. Next, issue the following four ADDRESS cycles: 00h-00h-01h-00h. Finally, issue the 10h command. R/B# goes LOW while the OTP area is being protected. The protect command duration is similar to a normal page programming operation, tPROG. The READ STATUS (70h) command is the only command valid during the OTP DATA PROTECT operation. Bit 5 of the status register will reflect the state of R/B#. When the device is ready, read bit 0 of the status register to determine if the operation passed or failed (see Table 9 on page 29). Figure 30: CLE OTP DATA PROTECT CE# tWC WE# tWB ALE tPROG RE# I/Ox A5h OTP DATA PROTECT Command Col 00h Col 00h 01h 00h 10h PROGRAM Command 70h READ STATUS Command Status OTP Address R/B# OTP Data Protected1 Don't Care Notes: 1. OTP data is protected following "good" status confirmation. PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. 2.0 6/06 EN 37 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Draft 6/ 28/ 2006 www..com Micron Confidential and Proprietary Advance 1Gb: x8, x16 NAND Flash Memory Command Definitions OTP DATA READ AFh-30h The OTP DATA READ (AFh-30h) command is used to read data from a page within the OTP area. An OTP page within the OTP area is available for reading data whether or not the area is protected. To use the OTP DATA READ command, issue the AFh command. Next, issue four ADDRESS cycles: the first two ADDRESS cycles are the column address, and for the remaining two cycles select a page in the range of 02h-0Bh. Finally, issue the 30h command. RANDOM DATA INPUT (05h-E0h) are supported during OTP DATA READ operations. R/B# goes LOW (tR) while the data is moved from the OTP page to the data register. The READ STATUS (70h) command and the RESET (FFh) command are the only commands valid during the OTP DATA READ operation. Bit 5 of the status register will reflect the state of R/B#. For details, refer to Table 9 on page 29. Normal READ operation timings apply to OTP read accesses (see Figure 31). Additional pages within the OTP area can be selected by repeating the OTP DATA READ command. Figure 31: CLE OTP DATA READ Operation CE# WE# ALE tR RE# I/Ox AFh Col Add 1 Col Add 2 OTP Page1 00h 30h DOUT N DOUT N+1 DOUT M OTP Address Busy R/B# Don't Care Notes: 1. The OTP page must be within the range 02h-0Bh. PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. 2.0 6/06 EN 38 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Draft 6/ 28/ 2006 www..com Micron Confidential and Proprietary Advance 1Gb: x8, x16 NAND Flash Memory Command Definitions Block Lock Feature The block lock feature of this NAND Flash device provides the ability to protect the entire device or ranges of blocks from PROGRAM and ERASE operations. Using this block lock feature offers increased functionality and flexibility over using just the WP# pin to prevent PROGRAM and ERASE operations. Block lock features are enabled and disabled at power-on through the use of the LOCK pin. At power-on, if LOCK is LOW, all block lock commands are disabled. However, at power-on, if LOCK is HIGH, the block lock commands are enabled and, by default, all of the blocks on the device are protected, or locked, from PROGRAM and ERASE operations, even if WP# is HIGH. Before the contents of the device can be modified, the device must first be unlocked. Either a range of blocks or the entire device can be unlocked. PROGRAM and ERASE operations complete successfully only in the block ranges that have been unlocked. Blocks, once unlocked, can be locked again to protect them from further PROGRAM and ERASE operations. Blocks that are locked can be protected further, or locked tight. When locked tight, the device's blocks can no longer be locked or unlocked until WP# is pulled LOW for more than 100ns. After WP# goes LOW for this period, the entire device is locked from PROGRAM and ERASE operations until unlocked again. WP# and Block Lock When the block lock feature is enabled, it interacts with WP# as follows: * The WP# pin must be driven HIGH and remain HIGH when UNLOCK and LOCKTIGHT commands are issued. * Holding WP# LOW locks all blocks. * If WP# is held LOW to lock blocks, then returned to HIGH, a new UNLOCK command must be issued to unlock blocks. UNLOCK 23h-24h By default at power-on if LOCK is HIGH, all of the blocks in the NAND Flash device are locked, meaning that they are protected from PROGRAM and ERASE operations. The UNLOCK (23h) command is used to unlock a range of blocks. Unlocked blocks have no protection and can be programmed or erased. The UNLOCK command uses two registers, a lower boundary block address register and an upper boundary block address register, and the invert area bit to determine what range of blocks are unlocked. When the invert area bit = 0, the range of blocks within the lower and upper boundary address registers are unlocked. When the invert area bit = 1, the range of blocks outside the boundaries of the lower and upper boundary address registers are unlocked. The lower boundary block address must be less than the upper boundary block address. Figures 32 and 33 on page 40 show examples of how the lower and upper boundary address registers work with the invert area bit. To unlock a range of blocks, issue the UNLOCK (23h) command followed by the appropriate ADDRESS cycles that indicate the lower boundary block address. Then issue the 24h command followed by the appropriate ADDRESS cycles that indicate the upper boundary block address. The least significant page address bit, PA0, should be set to "1" if setting the invert area bit; otherwise, it should be "0." The other page address bits should be "0" (see Figure 34 on page 41). Only one range of blocks can be specified in the lower and upper boundary block address registers. If after unlocking a range of blocks the UNLOCK command is again issued, the new block address range determines which blocks are unlocked. The previous unlocked block address range is not retained. PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. 2.0 6/06 EN 39 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Draft 6/ 28/ 2006 www..com Micron Confidential and Proprietary Advance 1Gb: x8, x16 NAND Flash Memory Command Definitions The UNLOCK (23h-24h) command is disabled if LOCK is LOW at power-on or if the device is locked tight (see page 43). Figure 32: Flash Array Protected: Inverted Area Bit = 0 Protected Area Figure 33: Flash Array Protected: Invert Area Bit = 1 Unprotected Area Block 1023 Block 1022 Block 1021 Block 1020 Block 1019 Block 1018 Block 1017 Block 1016 Block. 1015 . . . . . . . . . . . . . Block 0002 Block 0001 Block 0000 FFCh Upper Block Boundary Protected Area FF8h Lower Block Boundary Unprotected Area Table 10: ALE Cycle First Second Block Lock Address Cycle Assignments I/O[15:8]1 LOW LOW I/O7 BA7 BA15 I/O6 BA6 BA14 I/O5 LOW BA13 I/O4 LOW BA12 I/O3 LOW BA11 I/O2 LOW BA10 I/O1 LOW BA9 I/O0 Invert Area Bit2 BA8 Notes: 1. I/O[15:8] is applicable only for x16 devices. 2. Invert area bit is applicable for 24h command; it can be LOW or HIGH for 23h command. PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. 2.0 6/06 EN 40 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Draft 6/ 28/ 2006 Block 1023 Block 1022 Block 1021 Block 1020 Block 1019 Block 1018 Block 1017 Block 1016 Block. 1015 . . . . . . . . . . . . . Block 0002 Block 0001 Block 0000 FFCh Upper Block Boundary Unprotected Area FF8h Lower Block Boundary Protected Area www..com Micron Confidential and Proprietary Advance 1Gb: x8, x16 NAND Flash Memory Command Definitions Figure 34: UNLOCK Operation CLE CE# WE# ALE RE# Block Add 1 Block Add 2 Block Add 1 Block Add 2 I/Ox 23h Unlock 24h Lower Boundary Upper Boundary PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. 2.0 6/06 EN 41 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Draft 6/ 28/ 2006 www..com Micron Confidential and Proprietary Advance 1Gb: x8, x16 NAND Flash Memory Command Definitions LOCK 2Ah By default at power-on, if LOCK is HIGH, all of the blocks in the NAND Flash device are locked, meaning that they are protected from PROGRAM and ERASE operations. If portions of the device are unlocked using the UNLOCK (23h) command, they can be locked again using the LOCK (2Ah) command. The LOCK command locks all of the blocks in the device. Locked blocks are write-protected from PROGRAM and ERASE operations. To lock all of the blocks in the device, issue the LOCK (2Ah) command. When a PROGRAM or ERASE operation is issued to a locked block, R/B# goes LOW for t LBSY. The PROGRAM or ERASE operation does not complete. The READ STATUS (70h) command reports bit 7 as "0," indicating that the block is protected. The LOCK (2Ah) command is disabled if LOCK is LOW at power-on or if the device is locked tight (see page 43). Figure 35: LOCK Operation CLE WE# I/Ox 2Ah LOCK Command PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. 2.0 6/06 EN 42 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Draft 6/ 28/ 2006 CE# www..com Micron Confidential and Proprietary Advance 1Gb: x8, x16 NAND Flash Memory Command Definitions LOCK-TIGHT 2Ch The LOCK-TIGHT (2Ch) command prevents locked blocks from being unlocked and also prevents unlocked blocks from being locked. When this command is issued, the UNLOCK (23h) and LOCK (2Ah) commands are disabled. This provides an additional level of protection to locked blocks from inadvertent PROGRAM and ERASE operations. To implement lock-tight in all of the locked blocks in the device, verify that WP# is HIGH and then issue the LOCK-TIGHT (2Ch) command. When a PROGRAM or ERASE operation is issued to a locked block that has also been locked tight, R/B# goes LOW for tLBSY. The PROGRAM or ERASE operation does not complete. The READ STATUS (70h) command reports bit 7 as "0," indicating that the block is protected. PROGRAM and ERASE operations complete successfully to blocks that were not locked at the time the LOCK-TIGHT command was issued. Once the LOCK-TIGHT command is issued, it cannot be disabled via a software command. The only way to disable the lock-tight status is either to hold WP# LOW for greater than 100ns or to power cycle the device. When the lock-tight status is disabled, all of the blocks become locked, the same as if the LOCK (2Ah) command were issued. The LOCK-TIGHT (2Ch) command is disabled if LOCK is LOW at power-on. WP# CLE CE# WE# I/Ox 2Ch LOCK-TIGHT Command PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. 2.0 6/06 EN 43 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Draft 6/ 28/ 2006 Figure 36: LOCK-TIGHT Operation www..com Micron Confidential and Proprietary Advance 1Gb: x8, x16 NAND Flash Memory Command Definitions Figure 37: PROGRAM/ERASE Issued to Locked or Locked-Tight Block tLBSY R/B# I/Ox PROGRAM or ERASE Address/Data Input Locked or Locked-Tight Block CONFIRM 70h READ STATUS 60h Figure 38: LOCKED-TIGHT BLOCKS to LOCKED BLOCKS Operation LOCK CE# > 100ns WP# Note: The device ensures exit from lock-tight mode if the WP# pulse is greater than 100ns. The device may exit lock-tight mode if WP# pulse is less than 100ns, however, this is not guaranteed. PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. 2.0 6/06 EN 44 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Draft 6/ 28/ 2006 www..com Micron Confidential and Proprietary Advance 1Gb: x8, x16 NAND Flash Memory Command Definitions BLOCK LOCK READ STATUS 7Ah The BLOCK LOCK READ STATUS (7Ah) command is used to determine the protection status of individual blocks. The ADDRESS cycles have the same format as shown in Table 10 on page 40; the invert area bit should be set LOW. On the falling edge of RE# the I/O pins output the block lock status register which contains the information on the protection status of the block. Table 11 shows how to interpret the block lock status register bits. The BLOCK LOCK READ STATUS (7Ah) command is disabled if LOCK is LOW at power-on. Table 11: Block Lock Status Register Bit Definitions I/O[7:3] X X X X I/O2 (Lock#) 0 0 1 1 I/O1 (LT#) 0 1 0 1 I/O0 (LT) 1 0 1 0 Block Lock Status Register Definitions Block is locked and device is locked-tight Block is locked and device is not locked-tight Block is unlocked and device is locked-tight Block is unlocked and device is not locked-tight Figure 39: BLOCK LOCK READ STATUS CLE CE# WE# tWHRIO ALE RE# I/Ox 7Ah BLOCK LOCK READ STATUS Add 1 Add 2 Status Block Address PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. 2.0 6/06 EN 45 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Draft 6/ 28/ 2006 www..com Micron Confidential and Proprietary Advance 1Gb: x8, x16 NAND Flash Memory Command Definitions Figure 40: BLOCK LOCK Flow Chart Power-up Power-up with LOCK HIGH Power-up with LOCK LOW (default) BLOCK LOCK Function Disabled Entire NAND Flash Array Locked LOCK-TIGHT Cmd with WP# and LOCK HIGH Entire NAND Flash Array Locked Tight WP# LOW >100ns UNLOCK Cmd with Invert Area Bit = 0 Unlocked Range LOCK Cmd Locked Range LOCK Cmd UNLOCK Cmd with Invert Area Bit = 1 Locked Range Unlocked Range Unlocked Range Locked Range UNLOCK Cmd with Invert Area Bit = 0 UNLOCK Cmd with Invert Area Bit = 0 UNLOCK Cmd with Invert Area Bit = 1 LOCK-TIGHT Cmd with WP# and LOCK HIGH LOCK-TIGHT Cmd with WP# and LOCK HIGH Unlocked Range Locked-Tight Range Unlocked Range Locked-Tight Range Unlocked Range Locked-Tight Range WP# LOW > 100ns WP# LOW > 100ns PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. 2.0 6/06 EN 46 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Draft 6/ 28/ 2006 UNLOCK Cmd with Invert Area Bit = 1 www..com Micron Confidential and Proprietary Advance 1Gb: x8, x16 NAND Flash Memory Command Definitions RESET Operation RESET FFh The RESET command is used to put the memory device into a known condition and to abort a command sequence in progress. READ, PROGRAM, and ERASE commands can be aborted while the device is in the busy state. The contents of the memory location being programmed or the block being erased are no longer valid. The data may be partially erased. The command register is cleared and is ready for the next command. The status register contains the value E0h when WP# is HIGH; otherwise it is written with a 60h value. R/B# goes LOW for tRST after the RESET command is written to the command register. See Figure 41 and Table 12 for details. The RESET command must be issued after power-on and before any other command is issued to the device. The device will be busy for a maximum of 1ms at this time. Figure 41: RESET Operation CLE CE# tWB WE# tRST R/B# I/O FF RESET Command Table 12: Condition WP# HIGH WP# LOW Status Register Contents After Reset Status Ready Ready and write protected Bit 7 1 0 Bit 6 1 1 Bit 5 1 1 Bit 4 0 0 Bit 3 0 0 Bit 2 0 0 Bit 1 0 0 Bit 0 0 0 Hex E0h 60h PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. 2.0 6/06 EN 47 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Draft 6/ 28/ 2006 www..com Micron Confidential and Proprietary Advance 1Gb: x8, x16 NAND Flash Memory Command Definitions Programmable Drive Strength PROGRAMMABLE I/O DRIVE STRENGTH B8h The B8h command is used to change the default I/O drive strength as shown in Figure 42. Drive strength should be selected based on expected memory bus loading. There are four allowable settings for the output drive strength, as shown in Table 13. The default drive strength is shown in Table 13. The device returns to the default drive strength mode after it is power cycled. Figure 42 shows how to write and read the drive strength. Refer toTable 14 on page 49 for unique timing parameters associated with the PROGRAMMABLE I/O DRIVE STRENGTH command. Note that the AC timing characteristics documented in Table 21 and Table 22 may need to be relaxed if the I/O drive strength is not set to "Full." Figure 42: Programmable I/O Drive Strength Command Sequence tCLSIO tCLHIO CLE tWHIO tWPIO WE# tWHRIO ALE tREAIO RE# tDSIO I/Ox B8h tDHIO I/O[7:0]2 tRPIO tWCIO I/O[7:0]1 Notes: 1. WRITE operation. 2. READ operation. Table 13: I/O Drive Strength Settings I/O7 X X X X I/O6 X X X X I/O5 X X X X I/O4 X X X X I/O3 0 0 1 1 I/O2 0 1 0 1 I/O1 X X X X I/O0 X X X X Drive Strength Full (default) Three-quarters One-half One-quarter Notes: 1. For WRITE operation, X = "Don't Care." For READ operation, X = "Undefined." 2. Timing parameters shown in Table 21 on page 56 and Table 22 on page 57 represent full drive setting. PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. 2.0 6/06 EN 48 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Draft 6/ 28/ 2006 CE# www..com Micron Confidential and Proprietary Advance 1Gb: x8, x16 NAND Flash Memory Command Definitions Table 14: Parameter CLE hold time CLE setup time Data hold time Data setup time RE# access time RE# pulse width Write cycle time WE# pulse width high WE# high to RE# low WE# pulse width Programmable I/O Drive Strength Register READ/WRITE Timing Symbol tCLHIO t Min 15 25 15 30 - 250 100 50 100 50 Max - - - - 250 - - - - - Unit ns ns ns ns ns ns ns ns ns ns Notes CLSIO t DHIO tDSIO t REAIO t RPIO t WCIO t WHIO tWHRIO t WPIO PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. 2.0 6/06 EN 49 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Draft 6/ 28/ 2006 www..com Micron Confidential and Proprietary Advance 1Gb: x8, x16 NAND Flash Memory Command Definitions WRITE PROTECT Operation The WRITE PROTECT feature protects the device against inadvertent PROGRAM and ERASE operations. All PROGRAM and ERASE operations are disabled when WP# is LOW. For WRITE PROTECT timing details, see Figures 43 through 46. Figure 43: ERASE Enable WE# tWW I/Ox 60h D0h WP# R/B# WE# tWW I/Ox 60h D0h WP# R/B# Figure 45: PROGRAM Enable WE# tWW I/Ox 80h 10h WP# R/B# PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. 2.0 6/06 EN 50 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Draft 6/ 28/ 2006 Figure 44: ERASE Disable www..com Micron Confidential and Proprietary Advance 1Gb: x8, x16 NAND Flash Memory Command Definitions Figure 46: PROGRAM Disable WE# tWW I/Ox 80h 10h WP# R/B# PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. 2.0 6/06 EN 51 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Draft 6/ 28/ 2006 www..com Micron Confidential and Proprietary Advance 1Gb: x8, x16 NAND Flash Memory Error Management Error Management Micron MT29F1Gxx NAND Flash devices are specified to have a minimum of 1,004 valid blocks (NVB) out of 1,024 total available blocks. This means the devices may have blocks that are invalid when they are shipped. An invalid block is one that contains one or more bad bits. Additional bad blocks may develop with use. However, the total number of available blocks will not fall below NVB. Although NAND Flash memory devices may contain bad blocks, they can be used quite reliably in systems that provide bad-block mapping, replacement, and error correction algorithms. This type of software environment ensures data integrity. Internal circuitry isolates each block from other blocks, so the presence of a bad block does not affect the operation of the rest of the NAND Flash device. The first block (physical block address 00h) for each CE# in Micron NAND Flash devices is guaranteed to be free of defects (up to 1,000 PROGRAM/ERASE cycles) when shipped from the factory. This provides a reliable location for storing boot code and critical boot information. Before NAND Flash devices are shipped from Micron, they are erased. The factory identifies invalid blocks before shipping by programming data other than FFh (x8) or FFFFh (x16) into the first spare location (column address 2,048 for x8 devices, or 1,024 for x16 devices) of the first or second page of each bad block. System software should check the first spare address on the first and second page of each block prior to performing any erase or formatting operations on the NAND Flash device. A bad block table can then be created, enabling system software to map around these areas. Factory testing is performed under worst-case conditions. Because blocks marked "bad" may be marginal, it may not be possible to recover this information if the block is erased. If the NAND Flash device is erased before these operations are performed, system software must determine which blocks are bad by writing and verifying valid information in each memory location in the device. After writing and verifying all locations, the device must be fully erased and checked to verify that each block has erased properly. Over time, some memory locations may fail to program or erase properly. In order to ensure that data is stored properly over the life of the NAND Flash device, certain precautions must be taken, such as: * Always check status after a WRITE or ERASE operation. * Use some type of error detection and correction algorithm to recover from single-bit errors. * Use a bad block replacement algorithm. PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. 2.0 6/06 EN 52 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Draft 6/ 28/ 2006 Micron Confidential and Proprietary www..com Advance 1Gb: x8, x16 NAND Flash Memory Electrical Characteristics Electrical Characteristics Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not guaranteed. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Table 15: Device MT29F1GxxABB MT29F1GxxABB MT29F1GxxABB Short circuit output current, I/Os VIN VCC TSTG Absolute Maximum Ratings by Device Symbol Supply voltage on any pin relative to VSS Storage temperature Min -0.6 -0.6 -65 Max +2.45 +2.45 +150 5 Unit V V C mA Table 16: Recommended Operating Conditions Symbol Commercial Extended MT29F1GxxABB tA tA Parameter/Condition Operating temperature VCC supply voltage Supply voltage Min 0 -40 1.65 0 Typ - - 1.8 0 Max 70 85 1.95 0 Units oC VCC VSS V V PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. 2.0 6/06 EN 53 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Draft 6/ 28/ 2006 oC www..com Micron Confidential and Proprietary Advance 1Gb: x8, x16 NAND Flash Memory Electrical Characteristics VCC Power Cycling Micron NAND Flash devices are designed to prevent data corruption during power transitions. VCC is internally monitored. When VCC goes below 1.5V, PROGRAM and ERASE functions are disabled. WP# provides additional hardware protection. WP# should be kept at VIL during power cycling. When VCC reaches 1.5V, a minimum of 10s should be allowed for the NAND Flash to initialize before executing any commands (see Figure 47). The RESET command must be issued after power-on and before any other command is issued to the device. The device will be busy for a maximum of 1ms at this time. Figure 47: AC Waveforms During Power Transitions 1.8V device: 1.5V CLE 1.8V device: 1.5V VCC HIGH LOCK1 WE# 10s I/Ox FFh 1ms R/B# (MAX) Don't Care Undefined Notes: 1. If the system requires the LOCK features to be enabled, then the LOCK pin must be HIGH during power-up. If the LOCK features are to be disabled, then the LOCK pin should be held LOW during power-up. PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. 2.0 6/06 EN 54 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Draft 6/ 28/ 2006 WP# www..com Micron Confidential and Proprietary Advance 1Gb: x8, x16 NAND Flash Memory Electrical Characteristics Table 17: Parameter Sequential READ current PROGRAM current ERASE current Standby current (TTL) Standby current (CMOS) Input leakage current Output leakage current Input high voltage Input low voltage, all inputs Output high voltage Output low voltage Output low current (R/B#) t DC and Operating Characteristics, VCC = 1.65V-1.95V Conditions CYCLE = 50ns, CE# = VIL, IOUT = 0mA - - CE# = VIH, WP# = 0V/VCC CE# = VCC - 0.2V, WP# = 0V/VCC VIN = 0V to VCC VOUT = 0V to VCC I/O [7:0], I/O [15:0], CE#, CLE, ALE, WE#, RE#, WP#, R/B#, LOCK - IOH = -100A IOL = 100A VOL = 0.1V Symbol ICC1 ICC2 ICC3 ISB1 ISB2 ILI ILO VIH VIL VOH VOL IOL Min - - - - - - - 0.8 x VCC -0.3 VCC - 0.1 - 3 Typ 10 10 10 - 10 - - - - - - 4 Max 20 20 20 1 50 10 10 VCC + 0.3 0.2 x VCC - 0.1 - Unit mA mA mA mA A A A V V V V mA Table 18: Parameter Valid Blocks Symbol NVB Device MT29F1GxxABB Min 1,004 Typ - Max 1,024 Unit Blocks Notes 1, 2 Valid block number Notes: 1. Invalid blocks are blocks that contain one or more bad bits. The device may contain bad blocks after shipping. Additional bad blocks may develop over time; however, the total number of available blocks will not drop below NVB during the endurance life of the device. Do not erase or program blocks marked "invalid" by the factory. 2. Block 00h (the first block) is guaranteed to be valid, and does not require error correction for up to 1,000 PROGRAM/ERASE cycles. Table 19: Description Capacitance Symbol CIN CIO Device MT29F1GxxABB MT29F1GxxABB Max 10 10 Unit pF pF Notes 1, 2 1, 2 Input capacitance Input/output capacitance (I/O) Notes: 1. These parameters are verified in device characterization and are not 100 percent tested. 2. Test conditions: Tc = 25C; f = 1 MHz; VIN = 0V. PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. 2.0 6/06 EN 55 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Draft 6/ 28/ 2006 www..com Micron Confidential and Proprietary Advance 1Gb: x8, x16 NAND Flash Memory Electrical Characteristics Table 20: Parameter Input pulse levels Input rise and fall times Input and output timing levels Output load MT29F1GxxABA Test Conditions Value 0.0V to 1.8V 5ns VCC/2 1 TTL GATE and CL = 30pF Notes MT29F1GxxABA 1, 2 Notes: 1. Verified on device characterization; not 100 percent tested. 2. Outputs tested at full drive strength. Table 21: Parameter AC Characteristics - Command, Data, and Address Input Symbol tADL tALH tALS tCH tCLH tCLS tCS tDH tDS tWC tWH tWP tWW Min 100 10 25 10 10 25 25 10 20 45 15 25 30 Max - - - - - - - - - - - - - Unit ns ns ns ns ns ns ns ns ns ns ns ns ns Notes 1 Notes: 1. Timing for tADL begins in the ADDRESS cycle, on the final rising edge of WE#, and ends with the first rising edge of WE# data output. PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. 2.0 6/06 EN 56 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Draft 6/ 28/ 2006 ALE to data start ALE hold time ALE setup time CE# hold time CLE hold time CLE setup time CE# setup time Data hold time Data setup time WRITE cycle time WE# pulse width HIGH WE# pulse width WP# setup time www..com Micron Confidential and Proprietary Advance 1Gb: x8, x16 NAND Flash Memory Electrical Characteristics Table 22: Parameter ALE to RE# delay CE# access time CE# HIGH to output High-Z CLE to RE# delay CE# HIGH to output hold Cache busy in PAGE READ CACHE MODE (first 31h) Cache busy in PAGE READ CACHE MODE (next 31h and 3Fh) Ouput High-Z to RE# LOW Busy time for PROGRAM ERASE on locked block Busy time for OTP DATA PROGRAM operation if OTP is protected Data transfer from Flash array to data register READ cycle time RE# access time RE# HIGH hold time RE# HIGH to output hold RE# HIGH to WE# LOW RE# HIGH to output High-Z RE# LOW to output hold RE# pulse width Ready to RE# LOW Reset time (READ/PROGRAM/ERASE/power-up) WE# HIGH to busy WE# HIGH to RE# LOW AC Characteristics - Normal Operation Symbol tAR t Min 10 - - 10 15 - t DCBSYR1 0 2 15 - 50 - 15 15 100 - 5 25 20 - - 80 Max - 45 45 - - 3 25 - 3 20 25 - 30 - - - 100 - - - 5/10/500/ 1,000 100 - Unit ns ns ns ns ns s s ns s s s ns ns ns ns ns ns ns ns ns s ns ns Notes 1 1 1,2 1 1 1 1 1,2 1 1 1 1, 3 1 1 1 1 1, 2 1 1 1 1, 4 1, 4, 5 1 CEA t CHZ tCLR t COH t DCBSYR1 t DCBSYR2 t IR tLBSY t OBSY tR tRC tREA tREH tRHOH tRHW tRHZ tRLOH tRP tRR tRST tWB tWHR Notes: 1. AC characteristics may need to be relaxed if I/O drive strength is not set to full. 2. Transition is measured 200mV from steady-state voltage with load. This parameter is sampled and not 100 percent tested. 3. When VCC is less than 1.7V down to 1.65V, tRC MIN is 60ns. 4. If RESET (FFh) command is loaded at ready state, the device goes busy for maximum 5s. 5. Do not issue a new command during tWB, even if R/B# is ready. Table 23: Parameter PROGRAM/ERASE Characteristics Symbol NOP BERS tCBSY tLPROG tPROG t Typ - 2 3 - 300 Max 8 3 700 - 700 Unit Cycle ms s - s Notes 1 2 3 Number of partial page programs Block erase time Busy time for cache program Last page program time Page program time Notes: 1. 2. 3. Eight total to the same page. CBSY MAX time depends on timing between internal program completion and data in. tLPROG = tPROG (last page) + tPROG (last - 1 page) - command load time (last page) address load time (last page) - data load time (last page). t PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. 2.0 6/06 EN 57 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Draft 6/ 28/ 2006 www..com Micron Confidential and Proprietary Advance 1Gb: x8, x16 NAND Flash Memory Timing Diagrams Timing Diagrams Figure 48: COMMAND LATCH Cycle CLE tCLS tCS tCLH tCH CE# tWP WE# tALS tALH ALE tDS tDH I/Ox COMMAND Don`t Care Note: The x16 devices must have I/O[15:8] set to "0." Figure 49: ADDRESS LATCH Cycle CLE tCLS tCS tWC CE# tWP WE# tALS ALE tDS I/Ox Address Don`t Care Undefined tDH tALH tWH Note: The x16 devices must have I/O[15:8] set to "0." PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. 2.0 6/06 EN 58 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Draft 6/ 28/ 2006 www..com Micron Confidential and Proprietary Advance 1Gb: x8, x16 NAND Flash Memory Timing Diagrams Figure 50: CLE tCLH INPUT DATA LATCH Cycle CE# tALS tCH ALE tWC tWP tWP tWP WE# tWH tDS tDH tDS tDH tDS tDH Don`t Care Note: DIN Final = 2,112 (x8) or 1,056 (x16). Figure 51: SERIAL ACCESS Cycle after READ tCEA CE# tREA tRP tREH tREA t REA1 tCOH tCHZ1 RE# t RHZ1 tRHZ1 tRHOH I/Ox DOUT tRR tRC DOUT DOUT R/B# Don`t Care Note: Transition is measured +/- 200mV from steady-state voltage with load. This parameter is sampled and not 100 percent tested. PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. 2.0 6/06 EN 59 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Draft 6/ 28/ 2006 I/Ox DIN 0 DIN 1 DIN Final1 www..com Micron Confidential and Proprietary Advance 1Gb: x8, x16 NAND Flash Memory Timing Diagrams Figure 52: SERIAL ACCESS Cycle After READ (EDO Mode) CE# tRR tRP tRC tREH tCHZ tCOH RE# tREA tCEA tREA tRLOH DOUT DOUT tRHZ tRHOH DOUT I/Ox R/B# Figure 53: READ STATUS Cycle tCLR CLE tCLS tCLH tCS CE# tWP tCH WE# tCEA tWHR tRP tCHZ tCOH RE# tRHZ tRHOH tDS tDH tIR tREA I/Ox 70h Status Output Don`t Care PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. 2.0 6/06 EN 60 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Draft 6/ 28/ 2006 Don't Care www..com Micron Confidential and Proprietary Advance 1Gb: x8, x16 NAND Flash Memory Timing Diagrams Figure 54: CLE tCLR PAGE READ Operation CE# tWC WE# tWB tAR ALE tRC RE# tRR tRHZ tR Busy R/B# Don`t Care Figure 55: CLE READ Operation with CE# "Don't Care" CE# RE# ALE tR R/B# WE# I/Ox 00h Address (4 Cycles) 30h Data Output tCEA CE# tREA RE# Don`t Care Out I/Ox PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. 2.0 6/06 EN 61 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Draft 6/ 28/ 2006 I/Ox 00h Col Add 1 Col Add 2 Row Add 1 Row Add 2 30h DOUT N DOUT N+1 DOUT M www..com Micron Confidential and Proprietary Advance 1Gb: x8, x16 NAND Flash Memory Timing Diagrams Figure 56: CLE tCLR RANDOM DATA READ Operation CE# WE# tWB tAR tWHR ALE tRC tREA RE# tRR I/Ox 00h Col Add 1 Col Add 2 Row Add 1 Row Add 2 30h tR DOUT N DOUT N+1 05h Col Add 1 Col Add 2 E0h DOUT M DOUT M+1 Column Address N R/B# Column Address M Busy Don't Care PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. 2.0 6/06 EN 62 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Draft 6/ 28/ 2006 www..com Figure 57: CLE PAGE READ CACHE MODE Timing Diagram, Part 1 of 2 PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. 2.0 6/06 EN tCLS tCLH tCS CE# tCH tWC WE# tCEA ALE tRC RE# tWB tDS tDH tR tRR tREA DOUT 0 DOUT 1 Page Address M DOUT 31h DOUT 0 Micron Confidential and Proprietary I/O[8:1] 00h Col Add 1 Col Add 2 Row Add 1 Row Add 2 Page Address M 30h 31h Column Address 00h R/B# tDCBSYR1 tDCBSYR2 Page Address M+1 Column Address 0 Column Address 0 63 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1 Continued to 1 of next page Don't Care 1Gb: x8, x16 NAND Flash Memory Timing Diagrams Advance Draft 6/ 28/ 2006 www..com Figure 58: CLE PAGE READ CACHE MODE Timing Diagram, Part 2 of 2 PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. 2.0 6/06 EN tCLS tCLH tCS CE# tCH WE# tCEA ALE tRC RE# tWB tDS tDH I/O[8:1] DOUT 31h Micron Confidential and Proprietary tRR tREA DOUT 0 DOUT 1 DOUT 31h DOUT 0 DOUT 1 DOUT 3Fh DOUT 0 DOUT 1 DOUT tDCBSYR2 R/B# Page Address M+1 tDCBSYR2 Page Address M+2 tDCBSYR2 Page Address M+x Column Address 0 64 1 Continued from 1 of previous page Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Column Address 0 Column Address 0 Don't Care 1Gb: x8, x16 NAND Flash Memory Timing Diagrams Advance Draft 6/ 28/ 2006 www..com Figure 59: CLE PAGE READ CACHE MODE Timing without R/B#, Part 1 of 2 PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. 2.0 6/06 EN tCLS tCLH tCS CE# tCH tWC WE# tCEA ALE tRC RE# Micron Confidential and Proprietary tDS tDH I/O[8:1] 00h tREA Col Add 1 Col Add 2 Row Add 1 Row Add 2 Page Address M 30h 70h Status 31h 70h Status 00h DOUT 0 DOUT 1 Page Address M DOUT 31h 70h Status 00h DOUT 0 Page Address M+1 Column Address 00h I/O 5 = 0, Cache Busy = 1, Cache Ready I/O 6 = 0, Cache Busy = 1, Cache Ready I/O 6 = 0, Cache Busy = 1, Cache Ready Column Address 0 Column Address 0 65 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1 Continued to 1 of next page Don't Care 1Gb: x8, x16 NAND Flash Memory Timing Diagrams Advance Draft 6/ 28/ 2006 www..com Figure 60: CLE PAGE READ CACHE MODE Timing without R/B#, Part 2 of 2 PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. 2.0 6/06 EN tCLS tCLH tCS tCH CE# WE# tCEA ALE tRC RE# Micron Confidential and Proprietary tDS tDH tREA I/O[8:1] DOUT 31h 70h Status 00h DOUT 0 DOUT 1 DOUT 31h 70h Status 00h DOUT 0 DOUT 1 DOUT 3Fh 70h Status 00h DOUT 0 DOUT 1 DOUT I/O 6 = 0, Cache Busy = 1, Cache Ready Page Address M+1 I/O 6 = 0, Cache Busy = 1, Cache Ready Page Address M+2 I/O 6 = 0, Cache Busy = 1, Cache Ready Page Address M+x Column Address 0 Column Address 0 Column Address 0 66 1 Continued from 1 of previous page Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Don't Care 1Gb: x8, x16 NAND Flash Memory Timing Diagrams Advance Draft 6/ 28/ 2006 www..com Micron Confidential and Proprietary Advance 1Gb: x8, x16 NAND Flash Memory Timing Diagrams Figure 61: CLE READ ID Operation CE# WE# tAR ALE RE# tWHR tREA I/Ox 90h 00h Address, 1 Cycle Byte 0 Manufacturer ID 1 Byte 1 Device ID 1 Byte 2 Don't Care Byte 31 Byte 4 Figure 62: CLE PROGRAM Operation with CE# "Don't Care" CE# WE# ALE I/Ox 80h Address (4 Cycles) Data Input Data Input 10h tCS tCH CE# tWP WE# Don`t Care PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. 2.0 6/06 EN 67 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Draft 6/ 28/ 2006 www..com Micron Confidential and Proprietary Advance 1Gb: x8, x16 NAND Flash Memory Timing Diagrams Figure 63: CLE PROGRAM PAGE Operation CE# tWC tADL WE# tWB ALE tPROG RE# I/O 80h SERIAL DATA INPUT Command Col Add 1 Col Add 2 Row Add 1 Row Add 2 DIN N DIN M 10h PROGRAM Command 70h READ STATUS Command Status R/B# x8 device: m = 2,112 byte x16 device: m = 1,056 byte Don`t Care Figure 64: CLE PROGRAM PAGE Operation with RANDOM DATA INPUT CE# tWC tADL tADL WE# tWB tPROG ALE RE# I/Ox 80h Col Add 1 Col Add 2 Row Add 1 Row Add 2 DIN N DIN N+1 85h Col Add 1 Col Add 2 DIN N DIN N+1 Serial Input 10h PROGRAM Command 70h READ STATUS Command Status SERIAL DATA INPUT Command Serial Input RANDOM DATA Column Address INPUT Command R/B# Don`t Care PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. 2.0 6/06 EN 68 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Draft 6/ 28/ 2006 1 up to m Byte Serial Input www..com Micron Confidential and Proprietary Advance 1Gb: x8, x16 NAND Flash Memory Timing Diagrams Figure 65: CLE INTERNAL DATA MOVE CE# tWC tADL WE# tWB tWB tPROG ALE RE# I/Ox 00h Col Add 1 Col Add 2 Row Add 1 Row Add 2 35h 85h tR Busy Col Add 1 Col Add 2 Row Add 1 Row Add 2 Data 1 Data N 10h 70h READ STATUS Command Status Busy R/B# INTERNAL DATA MOVE Don`t Care Figure 66: CLE PROGRAM PAGE CACHE MODE CE# tWC WE# tADL tADL tWB tCBSY ALE tWB tPROG RE# Col Add 2 Row Add 1 Row Add 2 Col Add 1 Col Add 2 Row Add 1 Row Add 2 I/Ox 80h SERIAL DATA INPUT Command Col Add 1 DIN N Serial Input DIN M 15h PROGRAM 80h DIN N DIN M 10h PROGRAM 70h Status R/B# MAX 63 times repeatable tCSBY: Max 700s Last Page Input and Program Don`t Care Note: PROGRAM PAGE CACHE MODE can only be used within a block. PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. 2.0 6/06 EN 69 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Draft 6/ 28/ 2006 www..com Figure 67: CLE PROGRAM PAGE CACHE MODE Ending on 15h PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. 2.0 6/06 EN CE# tWC WE# tADL ALE RE# I/Ox 80h SERIAL DATA INPUT Col Add 1 Col Add 2 Row Add 1 Row Add 2 DIN N DIN M 15h 70h Status 80h Col Add 1 Col Add 2 Row Add 1 Row Add 2 Row Add 3 DIN N DIN M 15h PROGRAM 70h Status 70h Status Serial Input PROGRAM Micron Confidential and Proprietary Last Page -1 Last Page Poll status until: I/O6 = 1, Ready To ensure PROGRAM success, last 2pages: I/O5 = 1, Ready I/O0 = 0, Last page PROGRAM successful I/O1 = 0, Last page -1 PROGRAM successful Don`t Care 70 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x8, x16 NAND Flash Memory Timing Diagrams Advance Draft 6/ 28/ 2006 www..com Micron Confidential and Proprietary Advance 1Gb: x8, x16 NAND Flash Memory Timing Diagrams Figure 68: BLOCK ERASE Operation CLE CE# tWC WE# tWB ALE# tBERS RE# I/O 60h Row Add 1 Row Add 2 D0h ERASE Command Busy 70h READ STATUS Command Status Row Address R/B# ERASE SETUP Command Don`t Care Figure 69: RESET Operation CLE CE# tWB WE# tRST R/B# I/O FF RESET Command PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. 2.0 6/06 EN 71 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Draft 6/ 28/ 2006 www..com Micron Confidential and Proprietary Advance 1Gb: x8, x16 NAND Flash Memory Package Dimensions Package Dimensions Figure 70: 63-Ball VFBGA Package 0.65 0.05 SEATING PLANE 0.10 C C 7.20 63X O0.45 SOLDER BALL DIAMETER REFERS TO POST REFLOW CONDITION. THE PREREFLOW DIAMETER IS 0.42 BALL A10 0.80 TYP BALL A1 ID SOLDER BALL MATERIAL: 96.5% Sn, 3%Ag, 0.5% Cu SOLDER MASK DEFINED BALL PADS: O0.40 SUBSTRATE MATERIAL: PLASTIC LAMINATE MOLD COMPOUND: EPOXY NOVOLAC BALL A1 ID BALL A1 8.80 C L 13.00 0.10 4.40 6.50 0.05 C L 3.60 10.50 0.10 5.25 0.05 1.00 MAX Note: All dimensions are in millimeters. (R) 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 prodmktg@micron.com www.micron.com Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. 2.0 6/06 EN 72 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Draft 6/ 28/ 2006 0.80 TYP www..com Micron Confidential and Proprietary Advance 1Gb: x8, x16 NAND Flash Memory Revision History Revision History Rev. 2.0, Advance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6/06 * * * * * * * * * "READs" on page 17: Updated description. Table 8 on page 26: Removed note 2. Table 9 on page 28: Removed table. "OTP DATA PROGRAM A0h-10h" on page 35: Updated fourth paragraph. "OTP DATA READ AFh-30h" on page 38: Updated third paragraph. "BLOCK LOCK READ STATUS 7Ah" on page 45: Updated second paragraph. Table 11 on page 45: Revised column headings. "VCC Power Cycling" on page 54 Updated description. Figure 47 on page 54: Revised diagram. Rev. 1.0, Advance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5/06 * Initial release. PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__3.fm - Rev. 2.0 6/06 EN 73 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Draft 6/ 28/ 2006 www..com Micron Technology, Inc. Quality & Reliability Assurance Dept Mail Stop 502 8000 S. Federal Way P.O. Box 6 Boise, Idaho 83707-0006 RE: RoHS Certification Micron Technology, Inc. certifies that our Pb-free die/wafer and component level products meet the requirements of the current DIRECTIVE 2002/95/EC, a.k.a. Restriction of Hazardous Substances (RoHS) Directive without exemptions. Micron's Pb-free products mentioned above contain less than the following amounts of the six RoHS banned substances: * * * * * * Less than 0.1% Lead - Pb Less than 0.1% Mercury - Hg Less than 0.01% Cadmium - Cd Less than 0.1% Hexavalent Chromium - Cr (VI) Less than 0.1% Polybrominated Biphenyls - PBB Less than 0.1% Polybrominated Diphenyl Ethers - PBDE Please note that our module level products do contain electronic ceramic passive parts that may use lead-oxides which are exempt from Directive 2002/95/EC (see Article 4, Section 2 and Section 7 of the Annex thereto). Further questions should be addressed to your local Micron sales representative. Micron Technology, Inc. Quality and Reliability Assurance Department Performance. Power. Reliability |
Price & Availability of MT29F1G08ABB
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |